Section master module (SMM)

Master module of a section contains the FADC unit to digitalize the analog signals from OMs and to primary process the data, control unit to manage 12 OMs, and Ethernet modem for data transfer. The FADC unit provides the analog-to-digital convertion of the OM’s waveforme signals. It has six 2-channel 8-bit convertors with discretization frequency 200 MHz. Thus each OM corresponds to a certain FADC channel. The digitalized signals are then processed by the FPGA (Field Programmable Gate Array, Xilinx Spartan 6), which is a part of the FADC unit. The FPGA software can be uploaded remotely and provides the operation, buffering, and primary data processing. The FPGA’s memory buffer allows to store the data within the 5 microseconds time window. In addition the FADC unit produces local trigger signals which are used in common trigger of the cluster.

It is shown on the Fig. how the digitilized signal from OM looks like.

In order to descrease the amount of data to be transferred, processed, and stored,
only valuable parts of the data like the high pick and its vicinity are selected with the
help of a special FPGA software. The parts are then stored in the buffer. These data
along with the FADC unit number, local time, and some other information form data
records transmitted in a special format to the central module of the cluster via the
Ethernet connection (TCP/IP).

 

The amplitude analyzer is connected to each FADC channel. It accumulates a monitor histogram — amplitude distribution of the signals exceeding the registration level. Such distributions allow to control the registration levels and the noise rates of the corresponding channels.